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3-231 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc7129 features n count resolution ......................................... 19,999 n resolution on 200 mv scale .......................... 10 m v n true differential input and reference n low power consumption ................... 500 m a at 9v n direct lcd driver for 4-1/2 digits, decimal points, low-battery indicator, and continuity indicator n overrange and underrange outputs n range select input ............................................ 10:1 n high common-mode rejection ratio ......... 110 db n external phase compensation not required general description the tc7129 is a 4-1/2 digit analog-to-digital converter (adc) that directly drives a multiplexed liquid crystal dis- play (lcd). fabricated in high-performance, low-power cmos, the tc7129 adc is designed specifically for high- resolution, battery-powered digital multimeter applications. the traditional dual-slope method of a/d conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full scale, and resolution down to 10 m v per count. the tc7129 includes features important to multimeter applications. it detects and indicates low-battery condition. a continuity output drives an annunciator on the display, and can be used with an external driver to sound an audible alarm. overrange and underrange outputs and a range- change input provide the ability to create auto-ranging instruments. for snapshot readings, the tc7129 includes a latch-and-hold input to freeze the present reading. this combination of features makes the tc7129 the ideal choice for full-featured multimeter and digital measurement applications. typical operating circuit 4-1/2 digit analog-to-digital converter with on-chip lcd drivers tc7129-5 10/18/96 ordering information pin temperature part no. layout package range tc7129ckw formed 44-pin pqfp 0 c to +70 c TC7129CLW 44-pin plcc 0 c to +70 c tc7129cpl normal 40-pin pdip 0 c to +70 c tc7129 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9v + tc04 low battery continuity v + 5 pf 120 khz 10 pf 0.1 f 20 k w 0.1 f 100 k w 1 f 0.1 f 150 k w 10 k w v + v in ? + + * note: rc network between pins 26 and 28 is not required. * 330 k w
3-232 telcom semiconductor, inc. absolute maximum ratings* supply voltage (v + to v C ) ............................................ 15v reference voltage (ref hi or ref lo) .............. v + to v C input voltage (in hi or in lo) (note 1) ................ v + to v C v disp ................................................v + to (dgnd C 0.3v) digital input, pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40 .......... dgnd to v + analog input, pins 25, 29, 30 ............................... v + to v C package power dissipation (t a 70 c) plastic dip ........................................................1.23w plcc ................................................................1.23w plastic qfp .......................................................1.00w operating temperature range .................... 0 c to +70 c notes: input voltages may exceed supply voltages, provided input current is limited to 400 m a. currents above this value may result in invalid display readings but will not destroy the device if limited to 1 ma. dissipation ratings assume device is mounted with all leads soldered to printed circuit board. *static-sensitive device. unused devices must be stored in conductive material. protect devices from static discharge and static fields. stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics: v + to v C = 9v, v ref = 1v, t a = +25 c, f clk = 120 khz, unless otherwise indicated. pin numbers refer to 40-pin dip. symbol parameter test conditions min typ max unit input zero input reading v in = 0v, 200 mv scale C 0000 0000 +0000 counts zero reading drift v in = 0v, 0 c < t a < +70 c 0.5 m v/ c ratiometric reading v in = v ref = 1000 mv, range = 2v 9997 9999 10000 counts range change accuracy v in = 0.1v on low range 0.9999 1.0000 1.0001 ratio 4 v in = 1v on high range re roll-over error Cv in = +v in = 199 mv 1 2 counts nl linearity error 200 mv scale 1 counts cmrr common-mode rejection ratio v cm = 1v, v in = 0v, 200 mv scale 110 db cmvr common-mode voltage range v in = 0v (v C ) +1.5 v 200 mv scale (v + ) C1 v e n noise (peak-to-peak value not v in = 0v 14 m v p-p exceeded 95% of time) 200 mv scale i in input leakage current v in = 0v, pins 32, 33 1 10 pa scale factor temperature v in = 199 mv, 0 c < t a < +70 c 2 7 ppm/ c coefficient external v ref = 0 ppm/ c power v com common voltage v + to pin 28 2.8 3.2 3.5 v common sink current d common = +0.1v 0.6 ma common source current d common = C0.1v 10 m a dgnd digital ground voltage v + to pin 36, v + to v C = 9v 4.5 5.3 5.8 v sink current d dgnd = +0.5v 1.2 ma supply voltage range v + to v C 6912v i s supply current excluding common current v + to v C = 9v 0.8 1.3 ma f clk clock frequency 120 360 khz v disp resistance v disp to v + 50 k w low-battery flag activation voltage v + to v C 6.3 7.2 7.7 v digital continuity comparator v out pin 27 = high 100 200 mv threshold voltages v out pin 27 = low 200 400 mv pull-down current pins 37, 38, 39 2 10 m a storage temperature range ................ C 65 c to +150 c lead temperature (soldering, 10 sec) ................. +300 c tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers
3-233 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 33 34 35 36 37 38 39 13 10 9 8 7 18 19 20 21 23 24 6543 144 2 22 43 42 41 40 25 26 27 28 32 14 31 15 30 16 29 17 11 12 TC7129CLW f 1 , e 1 , dp 1 b 2 , c 2 , batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3, minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4, bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 nc ref lo ref hi in hi in lo buff c ref c + ref com cont int out nc a 1 , g 1 , d 1 b 1 , c 1 , cont a.d. osc 3 osc 1 nc osc 2 dp 1 dp 2 range dgnd bp 3 bp 2 bp 1 v disp dp 4 /or nc dp 3 /ur latch/hold v + v int in 27 28 29 30 31 32 33 7 4 3 2 1 tc7129ckw 12 13 14 15 17 18 44 43 42 41 39 38 40 16 37 36 35 34 19 20 21 22 26 8 25 9 24 10 23 11 5 6 a 1 , g 1 , d 1 b 1 , c 1 , cont a.d. osc 3 osc 1 nc osc 2 dp 1 dp 2 range dgnd ref lo ref hi in hi in lo buff c ref c + ref com cont int out nc f 1 , e 1 , dp 1 b 2 , c 2 , batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3, minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4, bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 nc bp 3 bp 2 bp 1 v disp dp 4 /or nc dp 3 /ur latch/hold v + v int in tc7129cpl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 osc 2 dp 1 dp 2 range dgnd ref lo ref hi in hi in lo buff c ref c + ref com cont int out int in v + v dp 3 /ur osc 1 osc 3 annunicator drive b 1 , c 1 , cont a 1 , g 1 , d 1 f 1 , e 1 , dp 1 b 2 , c 2 , lo batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3, minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4, bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 bp 3 bp 2 bp 1 v disp dp 4 /or display output lines latch/hold pin configurations 44-pin plcc 44-pin qfp 40-pin pdip "weak output" current pins 20, 21 sink/source 3/3 m a sink/source pin 27 sink/source 3/9 m a pin 22 source current 40 m a pin 22 sink current 3 m a symbol parameter test conditions min typ max unit electrical characteristics: v + to v C = 9v, v ref = 1v, t a = +25 c, f clk = 120 khz, unless otherwise indicated. pin numbers refer to 40-pin dip. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers
3-234 telcom semiconductor, inc. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers pin descriptions pin no. pin no. pin no. 40-pin 44-pin 44-pin tc7129cpl tc7129ckw TC7129CLW symbol function 1 40 2 osc 1 input to first clock inverter. 2 41 3 osc 3 output of second clock inverter. 3 annunciator backplane square-wave output for driving annunciators. 4435b 1 , c 1 , cont output to display segments. 5446a 1 , g 1 , d 1 output to display segments. 617f 1 , e 1 , dp 1 output to display segments. 728b 2 , c 2 , lo batt output to display segments. 839a 2 , g 2 , d 2 output to display segments. 9410f 2 , e 2 , dp 2 output to display segments. 10 5 11 b 3 , c 3 , minus output to display segments. 11 7 13 a 3 , g 3 , d 3 output to display segments. 12 8 14 f 3 , e 3 , dp 3 output to display segments. 13 9 15 b 4 , c 4 , bc 5 output to display segments. 14 10 16 a 4 , d 4 , g 4 output to display segments. 15 11 17 f 4 , e 4 , dp 4 output to display segments. 16 12 18 bp 3 backplane #3 output to display. 17 13 19 bp 2 backplane #2 output to display. 18 14 20 bp 1 backplane #1 output to display. 19 15 21 v disp negative rail for display drivers. 20 16 22 dp 4 /or input: when hi, turns on most significant decimal point. output: pulled hi when result count exceeds 19,999. 21 18 24 dp 3 /ur input: second most significant decimal point on when hi. output: pulled hi when result count is less than 1000. 22 19 25 latch/hold input: when floating, adc operates in the free-run mode. when pulled hi, the last displayed reading is held. when pulled lo, the result counter contents aren shown inincrementing during the deintegrate phase of cycle. output: negative-going edge occurs when the data latches are updated. can be used for converter status signal. 23 20 26 v C negative power supply terminal. 24 27 v + positive power supply terminal and positive rail for display drivers. 25 21 28 int in input to integrator amplifier. 26 23 29 int out output of integrator amplifier. 27 24 30 continuity input: when lo, continuity flag on the display is off. when hi, continuity flag is on. output: hi when voltage between inputs is less than +200 mv. lo when voltage between inputs is more than +200 mv. 28 25 31 common sets common-mode voltage of 3.2v below v + for de, 10x, etc. can be used as preregulator for external reference. 29 26 32 c + ref positive side of external reference capacitor. 30 27 33 c C ref negative side of external reference capacitor. 31 29 35 buffer output of buffer amplifier. 32 30 36 in lo negative input voltage terminal. 33 31 37 in hi positive input voltage terminal.
3-235 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 pin descriptions pin no. pin no. pin no. 40-pin 44-pin 44-pin tc7129cpl tc7129ckw TC7129CLW symbol function 34 32 38 ref hi positive reference voltage in 35 33 39 ref lo negative reference voltage 36 34 40 dgnd internal ground reference for digital section. see " 5v power supply" paragraph. 37 35 41 range 3 m a pull-down for 200 mv scale. pulled hi externally for 2v scale. 38 36 42 dp 2 internal 3 m a pull-down. when hi, decimal point 2 will be on. 39 37 43 dp 1 internal 3 m a pull-down. when hi, decimal point 1 will be on. 40 38 44 osc 2 output of first clock inverter. input of second clock inverter. 6,17, 28, 39 12, 23, 34,1 nc no connection component selection (all pin designations refer to 40-pin dip) the tc7129 is designed to be the heart of a high- resolution analog measurement instrument. the only addi- tional components required are a few passive elements, a voltage reference, an lcd, and a power source. most component values are not critical; substitutes can be chosen based on the information given below. the basic circuit for a digital multimeter application is shown in figure 1. see "special applications" for variations. typical values for each component are shown. the sections below give component selection criteria. oscillator (x osc , c o1 , c o2 , r o ) the primary criterion for selecting the crystal oscillator is to chose a frequency that achieves maximum rejection of line-frequency noise. to do this, the integration phase should last an integral number of line cycles. the integration phase of the tc7129 is 10,000 clock cycles on the 200 mv range and 1000 clock cycles on the 2v range. one clock cycle is equal to two oscillator cycles. for 60 hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2v range: 1/60 second = 16.7 msec = 1000 clock cycles 2 osc cycles/clock cycle oscillator frequency giving an oscillator frequency of 120 khz. a similar calcula- tion gives an optimum frequency of 100 khz for 50 hz rejection. * , the resistor and capacitor values are not critical; those shown work for most applications. in some situations, the capacitor values may have to be adjusted to compensate for parasitic capacitance in the circuit. the capacitors can be low-cost ceramic devices. some applications can use a simple rc network instead of a crystal oscillator. the rc oscillator has more potential for jitter, especially in the least significant digit. see "rc oscillator." integrating resistor (r int ) the integrating resistor sets the charging current for the integrating capacitor. choose a value that provides a current between 5 m a and 20 m a at 2v, the maximum full- scale input. the typical value chosen gives a charging current of 13.3 m a: i charge = 13.3 m a too high a value for r int increases the sensitivity to noise pickup and increases errors due to leakage current. too low a value degrades the linearity of the integration, leading to inaccurate readings. 2v 150 k w tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers
3-236 telcom semiconductor, inc. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers figure 1. standard circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9v + tc04 low battery continuity v + 5 pf 120 khz 10 pf 0.1 ? 20 k w 0.1 ? 100 k w c int 0.1 ? v + v in ?+ + 330 k w crystal r o c o2 c rf d ref r ref c if r if c ref 1 ? 10 k w r bias 150 k w r int osc 1 osc 3 annunc v disp dp 4 /or display drive outputs dp 3 /ur latch/ hold v v + int in int out continuity common c ref + c ref buffer in lo in hi ref hi ref lo dgnd range dp 2 dp 1 osc 2 tc7129 c o1
3-237 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers integrating capacitor (c int ) the charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. the primary selection criterion for c int is to choose a value that gives the highest voltage swing while remain- ing within the high-linearity portion of the integrator output range. an integrator swing of 2v is the recommended value. the capacitor value can be calculated from the equation: c int = , where t int is the integration time. using the values derived above (assuming 60 hz operation), the equation becomes: c int = = 0.1 m f. the capacitor should have low dielectric absorption to ensure good integration linearity. polypropylene and teflon capacitors are usually suitable. a good measurement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: pin to pin 20 ? 33 (c ref + to in hi) 30 ? 32 (c ref C to in lo) a reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric ab- sorption. reference capacitor (c ref ) the reference capacitor stores the reference voltage during several phases of the measurement cycle. low leakage is the primary selection criterion for this component. the value must be high enough to offset the effect of stray capacitance at the capacitor terminals. a value of at least 1 m f is recommended. voltage reference (d ref , r ref , r bias , c rf ) a tc04 band-gap reference provides a high-stability voltage reference of 1.25v. the reference potentiometer (r ref ) provides an adjustment for adjusting the reference voltage; any value above 20 k w is adequate. the bias resistor (r bias ) limits the current through d ref to less than 150 m a. the reference filter capacitor (c rf ) forms an rc filter with r bias to help eliminate noise. input filter (r if , c if ) for added stability, an rc input noise filter is usually included in the circuit. the input filter resistor value should not exceed 100 k w . a typical rc time constant value is 16.7msec to help reject line-frequency noise. the input filter capacitor should have low leakage for a high-impedance input. battery the typical circuit uses a 9v battery as a power source. any value between 6v and 12v can be used. for operation from batteries with voltages lower than 6v and for operation from power supplies, see "powering the tc7129." special applications the tc7129 as a replacement part the tc7129 is a direct pin-for-pin replacement part for the icl7129. note, however, that part requires a capacitor and resistor between pins 26 and 28 for phase compensa- tion. since the tc7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation. powering the tc7129 while the most common power source for the tc7129 is a 9v battery, there are other possibilities. some of the more common ones are explained below. 16.7msec x 13.3 m a 2v t int x i int v swing
3-238 telcom semiconductor, inc. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers figure 2. powering the tc7129 from a 5v power supply v v + ref hi ref lo in hi com in lo dgnd v in + ?v 0.1 ? +5v 0.1 ? 24 34 35 28 33 32 23 36 tc7129 tc04 0.1 ? 5v power supply measurements are made with respect to power supply ground. dgnd (pin 36) is set internally to about 5v less than v + (pin 24); it is not intended as a power supply input and must not be tied directly to power supply ground. (it can be used as a reference for external logic, as explained in "connecting to external logic." (see figure 2.) v tc7129 v ref hi ref lo in hi com in lo dgnd 3.8v to 6v + + 10 ? + 8 2 4 10 ? tc04 + 3 tc7660 v in 5 24 + 34 35 28 33 32 23 36 figure 3. powering the tc7129 from a low-voltage battery v v dgnd + 10 ? + 8 2 4 10 ? tc04 + 3 v in 5 24 + 34 35 28 33 32 23 36 tc7660 v + gnd 0.1 ? 0.1 ? + 5v tc7129 figure 4. powering the tc7129 from a +5v power supply low-voltage battery source a battery with voltage between 3.8v and 6v can be used to power the tc7129 when used with a voltage-doubler circuit as shown in figure 3. the voltage doubler uses the tc7660 dc-to-dc voltage converter and two external ca- pacitors. +5v power supply measurements are made with respect to power supply ground. common (pin 28) is connected to ref lo (pin 35). a voltage doubler is needed, since the supply voltage is less than the 6v minimum needed by the tc7129. dgnd (pin 36) must be isolated from power supply ground. (see figure 4.) connecting to external logic external logic can be directly referenced to dgnd (pin 36), provided that the supply current of the external logic does not exceed the sink current of dgnd (figure 5). a safe value for dgnd sink current is 1.2 ma. if the sink current is expected to exceed this value, a buffer is recommended. (see figure 6.)
3-239 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 figure 5. external logic referenced directly to dgnd figure 6. external logic referenced to dgnd with buffer temperature compensation for most applications, v disp (pin 19) can be connected directly to dgnd (pin 36). for applications with a wide temperature range, some lcds require that the drive levels vary with temperature to maintain good viewing angle and display contrast. figure 7 shows two circuits that can be adjusted to give temperature compensation of about 10 mv/ c between v + (pin 24) and v disp . the diode between dgnd and v disp should have a low turn-on voltage be- cause v disp cannot exceed 0.3v below dgnd. external logic dgnd v + 36 24 23 i logic tc7129 v + external logic i logic dgnd 23 24 v + 36 tc7129 v tc7129 + 1n4148 5 k w 75 k w 200 k w 39 k w 19 36 24 23 v v + v disp dgnd tc7129 2n2222 39 k w 19 36 24 23 v v + v disp dgnd 20 k w 18 k w figure 7. temperature compensating circuits tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers
3-240 telcom semiconductor, inc. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers rc oscillator for applications in which 3-1/2 digit (100 m v) resolution is sufficient, an rc oscillator is adequate. a recommended value for the capacitor is 51 pf. other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. the resistor value is calculated from: r = for 120 khz frequency and c = 51 pf, the calculated value of r is 75 k w . the rc oscillator and the crystal oscillator circuits are shown in figure 8. measuring techniques two important techniques are used in the tc7129: successive integration and digital auto-zeroing. successive integration is a refinement to the traditional dual-slope conversion technique. dual-slope conversion a dual-slope conversion has two basic phases: inte- grate and deintegrate. during the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. during the deintegrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. the count is a figure 8. oscillator circuits 0.45 freq c * measurement of the time to ramp the integrated voltage to zero, and is therefore proportional to the input voltage being measured. this count can then be scaled and displayed as a measurement of the input voltage. figure 9 shows the phases of the dual-slope conversion. the dual-slope method has a fundamental limitation. the count can only stop on a clock cycle, so that measure- ment accuracy is limited to the clock frequency. in addition, a delay in the zero-crossing comparator can add to the inaccuracy. figure 10 shows these errors in an actual measurement. successive integration the successive integration technique picks up where dual-slope conversion ends. the overshoot voltage shown in figure 10, called the "integrator residue voltage," is measured to obtain a correction to the initial count. figure 11 shows the cycles in a successive integration measurement. the waveform shown is for a negative input signal. the sequence of events during the measurement cycle is: phase description int 1 input signal is integrated for fixed time. (1000 clock cycles on 2v scale, 10,000 on 200 mv) de 1 integrator voltage is ramped to zero. counter counts up until zero crossing to produce reading accurate to 3-1/2 digits. residue represents an overshoot of the actual input voltage. rest rest; circuit settles. x10 residue voltage is amplified 10 times and inverted. de 2 integrator voltage is ramped to zero. counter counts down until zero crossing to correct reading to 4-1/2 digits. residue represents an undershoot of the actual input voltage. rest rest; circuit settles. x10 residue voltage is amplified 10 times and inverted. de 3 integrator voltage is ramped to zero. counter counts up until zero crossing to correct reading to 5-1/2 digits. residue is discarded. figure 9. dual-slope conversion deintegrate zero crossing time integrate tc7129 tc7129 1 40 2 270 k w 10 pf v + 120 khz 5 pf v + 1 40 2 51 pf 75 k w
3-241 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 integrate deintegrate time clock pulses overshoot due to zero crossing between clock pulses integrator residue voltage overshoot caused by comparator delay of 1 clock pulse figure 10. accuracy errors in dual-slope conversion figure 11. integrator waveform int 1 integrate de 1 deintegrate rest x10 zero integrate and latch de 2 rest x10 de 3 zero integrate integrator residual voltage tc7129 note: shaded area greatly expanded in time and amplitude. inside the tc7129 figure 12 shows a simplified block diagram of the tc7129. integrator section the integrator section includes the integrator, compara- tor, input buffer amplifier, and analog switches used to change the circuit configuration during the separate mea- surement phases described earlier. digital auto-zeroing to eliminate the effect of amplifier offset errors, the tc7129 uses a digital auto-zeroing technique. after the input voltage is measured as described above, the mea- surement is repeated with the inputs shorted internally. the reading with inputs shorted is a measurement of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other adcs. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers
3-242 telcom semiconductor, inc. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers low battery continuity segment drives backplane drives latch, decode display multiplexer up/down results counter sequence counter/decoder control logic analog section osc 1 osc 2 osc 3 range l/h cont v + v dgnd common in hi in lo buff dp 1 dp 2 ur/dp 3 or/dp 4 ref hi ref lo int out int in annunciator drive v disp tc7129 figure 12. functional block diagram
3-243 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers figure 13. integrator block diagram the buffer amplifier has a common-mode input voltage range from 1.5v above v C to 1v below v + . the integrator amplifier can swing to within 0.3v of the rails, although for best linearity the swing is usually limited to within 1v. both amplifiers can supply up to 80 m a of output current, but should be limited to 20 m a for good linearity. continuity indicator a comparator with a 200 mv threshold is connected between in hi (pin 33) and in lo (pin 32). whenever the voltage between inputs is less than 200 mv, the continuity output (pin 27) will be pulled high, activating the continuity annunciator on the display. the continuity pin can also be used as an input to drive the continuity annunciator directly from an external source. a schematic of the input/output nature of this pin is shown in figure 15. figure 14. continuity indicator circuit com buffer 200 mv in hi + in lo + v cont 500 k w to display driver (not latched) tc7129 common ref hi buffer inte- grator de zi, x10 comparator 1 200 mv c ref r int c int int 1 in hi + + + ref lo de in lo + de de+ de+ de 100 pf v + continuity int 1, int 2 continuity comparator 500 k w rest to display driver 10 pf comparator 2 to digital section tc7129 int x10 table i. switch legends label meaning de open during all deintegrate phases. deC closed during all deintegrate phases when input voltage is negative. de+ closed during all deintegrate phases when input voltage is positive. int 1 closed during the first integrate phase (measurement of the input voltage). int 2 closed during the second integrate phase (measurement of the amplifier offset). int open during both integrate phases. rest closed during the rest phase. zi closed during the zero-integrate phase. x10 closed during the x10 phase. x10 open during the x10 phase.
3-244 telcom semiconductor, inc. sequence and results counter a sequence counter and associated control logic pro- vide signals that operate the analog switches in the integra- tor section. the comparator output from the integrator gates the results counter. the results counter is a six-section up/ down decade counter which holds the intermediate results from each successive integration. overrange and underrange outputs when the results counter holds a value greater than 19,999, the dp 4 /or output (pin 20) is driven high. when the results counter value is less than 1000, the dp 3 /ur output (pin 21) is driven high. both signals are valid on the falling edge of latch/hold (l/h) and do not change until the end of the next conversion cycle. the signals are updated at the end of each conversion unless the l/h input (pin 22) is held high. pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. figure 15 shows a schematic of the input/output nature of these pins. latch/hold the l/h output goes low during the last 100 cycles of each conversion. this pulse latches the conversion data into the display driver section of the tc7129. this pin can also be used as an input. when driven high, the display will not be updated; the previous reading is displayed. when driven low, the display reading is not latched; the sequence counter reading will be displayed. since the counter is counting much faster than the backplanes are being up- dated, the reading shown in this mode is somewhat erratic. display driver the tc7129 drives a triplexed lcd with three back- planes. the lcd can include decimal points, polarity sign, and annunciators for continuity and low battery. figure 17 shows the assignment of the display segments to the backplanes and segment drive lines. the backplane drive frequency is obtained by dividing the oscillator frequency by 1200. this results in a backplane drive frequency of 100 hz for 60 hz operation (120 khz crystal) and 83.3 hz for 50 hz operation (100 khz crystal). backplane waveforms are shown in figure 18. these appear on outputs bp 1 , bp 2 , bp 3 (pins 16, 17, and 18). they remain the same regardless of the segments being driven. other display output lines (pins 4 through 15) have waveforms that vary depending on the displayed values. figure 19 shows a set of waveforms for the a, g, d outputs (pins 5, 8, 11, and 14) for several combinations of "on" segments. tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers + 12 ? p tc7129 logic section 5v 3.2v n n v + v com dgnd 24 28 36 23 tc7129 ' 500 k w dp 4 /or, pin 20 dp 3 /ur, pin 21 latch/hold pin 22 continuity, pin 27 figure 15. input/output pin schematic common and digital ground the common and digital ground (dgnd) outputs are generated from internal zener diodes. the voltage between v + and dgnd is the internal supply voltage for the digital section of the tc7129. common can source approximately 12 m a; dgnd has essentially no source capability. low battery the low battery annunciator turns on when supply voltage between v + and v C drops below 6.8v. the internal zener has a threshold of 6.3v. when the supply voltage drops below 6.8v, the transistor tied to v C turns off, pulling the "low battery" point high. (see figure 16.) figure 16. digital ground (dgnd) and common outputs
3-245 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 figure 17. display segment assignments the annunciator drive output (pin 3) is a square- wave running at the backplane frequency (100 hz or 83.3 hz), with a peak-to-peak voltage equal to dgnd voltage. con- necting an annunciator to pin 3 turns it on; connecting it to its backplane turns it off. figure 18. backplane waveforms bp 1 bp 2 bp 3 low battery low battery continuity f 4, e 4, dp 4 a 4, g 4, d 4 b 4, c 4, bc 4 f 3, e 3, dp 3 a 3, g 3, d 3 b 3, c 3, minus b 1, c 1, continuity a 1, g 1, d 1 f 1, e 1, dp 1 b 2, c 2, low battery a 2, g 2, d 2 backplane connections f 2, e 2, dp 2 continuity bp 1 bp 2 bp 3 figure 19. typical display output waveforms v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp b segment line all off a segment on d, g off a, g on d off all on tc7129 4-1/2 digit analog-to-digital converter with on-chip lcd drivers

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